Browsing by Author "Sousa, Ricardo M."
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- Full image-processing pipeline in field-programmable gate array for a small endoscopic cameraPublication . Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, João; Wäny, Martin; Dias, F. MorgadoEndoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm × 1 mm × 1.65 mm is used. Due to the physical prop erties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.
- On the implementation of the gamma function for image correction on a endoscopic cameraPublication . Mostafa, Sheikh Shanawaz; Sousa, L. Natercia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, João; Dias, F. Morgado; Wany, MartinThis paper describes part of project that implemented the image processing of a CMOS sensor for endoscopic purposes. The sensor is a small sized device of 1x1mm2 and the image processing has been done inside a FPGA. This part of the work describes the implementation of the Gamma function with a balance between the resources needed and the accuracy. A linear piecewise solution was used that stores the values for 31 gamma functions with values ranging from 1 to 4 with 0.1 steps. The solution developed is 10 bit based, was coded in VHDL and is implemented in a Spartan 6 FPGA. The results show that it is an accurate solution that has a small footprint in terms of used resources.