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Este trabalho apresenta o desenvolvimento de um conversor analógico-digital
(Analog-Digital Converter, ADC) de aproximações sucessivas (Successive Approximation Register, SAR) de alta velocidade e precisão, destinado à integra ção em sensores de imagem CMOS (Metal-Óxido-Semicondutor Complementar). A
arquitetura do ADC foi otimizada para obter rápida conversão e elevada exatidão,
adequando-se às exigências de sistemas de captura de imagem modernos. O pro jeto incluiu o dimensionamento e implementação, ao nível do transístor, dos princi pais blocos funcionais do ADC SAR, nomeadamente um conversor digital-analógico
(Digital-Analog Converter, DAC) de rede resistiva, um comparador dinâmico de
baixo consumo e a lógica de controlo SAR, em tecnologia CMOS de 65 nm. Adi cionalmente, integrou-se a técnica de amostragem dupla correlacionada (Correlated
Double Sampling, CDS) no sistema, permitindo mitigar o ruído e o offset do sinal
proveniente do ADC. As simulações do circuito foram realizadas no ambiente Ca dence Virtuoso. Os resultados obtidos demonstram que o ADC atingiu um tempo
de conversão de aproximadamente 0,4 µs por amostra (cerca de 2,5 MS/s) para uma
resolução de 10 bits, com consumo de potência na ordem de 1 mW. Verificou-se uma
elevada linearidade estática, com DNL (Diferential Non-Linearity) e INL (Integral
Non-Linearity) inferiores a ±0,25 LSB (Least Significant Bit), sem códigos faltantes.
A implementação da técnica CDS revelou-se eficaz, sendo possível eliminar o offset
previamente presente no sistema, conforme comprovado pelos resultados obtidos.
This work presents the development of a high-speed and high-precision Successive Approximation Analog-to-Digital Converter (SAR ADC), designed for integration in CMOS (Complementary Metal-Oxide Semiconductor) image sensors. The ADC’s architecture was optimized to achieve fast conversion and high accuracy, meeting the demands of image capture systems. The project involved transistor-level implemen tation of the main SAR ADC blocks, including a resistor-string Digital-to-Analog Converter (DAC), a low-power dynamic comparator, and SAR control logic, using 65 nm CMOS technology. The Correlated Double Sampling (CDS) technique was also integrated into the system to reduce noise and offset. Circuit simulations were carried out using the Cadence Virtuoso environment. The results show that the ADC achieved a conversion time of 0.4 µs per sample (approximately 2.5 MS/s) with 10-bit resolution and a power consumption close 1 mW. Excellent static line arity was verified, with DNL (Differential Non-Linearity) and INL (Integral Non Linearity) within ±0.25 LSB (Least Significant Bit) and no missing codes. The implementation of the CDS technique proved effective, successfully eliminating the offset previously present in the system and contributing to the overall performance of the converter.
This work presents the development of a high-speed and high-precision Successive Approximation Analog-to-Digital Converter (SAR ADC), designed for integration in CMOS (Complementary Metal-Oxide Semiconductor) image sensors. The ADC’s architecture was optimized to achieve fast conversion and high accuracy, meeting the demands of image capture systems. The project involved transistor-level implemen tation of the main SAR ADC blocks, including a resistor-string Digital-to-Analog Converter (DAC), a low-power dynamic comparator, and SAR control logic, using 65 nm CMOS technology. The Correlated Double Sampling (CDS) technique was also integrated into the system to reduce noise and offset. Circuit simulations were carried out using the Cadence Virtuoso environment. The results show that the ADC achieved a conversion time of 0.4 µs per sample (approximately 2.5 MS/s) with 10-bit resolution and a power consumption close 1 mW. Excellent static line arity was verified, with DNL (Differential Non-Linearity) and INL (Integral Non Linearity) within ±0.25 LSB (Least Significant Bit) and no missing codes. The implementation of the CDS technique proved effective, successfully eliminating the offset previously present in the system and contributing to the overall performance of the converter.
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Sensor de imagem CMOS ADC SAR CDS Image sensor Engenharia Eletrotécnica - Telecomunicações . Faculdade de Ciências Exatas e da Engenharia